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si827x data sheet 4 amp isodriver with high transient (dv/dt) immunity the si827x isolators are ideal for driving power switches used in a wide variety of power supply, inverter, and motor control applications. the si827x isolated gate drivers utilize silicon laboratories' proprietary silicon isolation technology, supporting up to 2.5 kvrms withstand voltage per ul1577 and vde0884. this technology enables industry leading common-mode transient immunity (cmti), tight timing specifications, reduced variation with temperature and age, better part-to-part matching, and extremely high reli- ability. it also offers unique features such as separate pull-up/down outputs, driver shut- down on uvlo fault, and precise dead time programmability. the si827x series offers longer service life and dramatically higher reliability compared to opto-coupled gate driv- ers. the si827x drivers utilize silicon labs' proprietary silicon isolation technology, which provides up to 2.5 kvrms withstand voltage per ul1577 and fast 60 ns propagation times. driver outputs can be grounded to the same or separate grounds or connected to a positive or negative voltage. the ttl level compatible inputs with >400 mv hysteresis are available in individual control input (si8271/2/3/5) or pwm input (si8274) configura- tions. high integration, low propagation delay, small installed size, flexibility, and cost- effectiveness make the si827x family ideal for a wide range of isolated mosfet/igbt and sic or gan fet gate drive applications. applications: ? switch-mode power supplies ? solar power inverters ? motor control and drives ? uninterruptible power supplies ? high-power class d amplifiers safety regulatory approvals (pending): ? ul 1577 recognized ? up to 2500 vrms for 1 minute ? csa component notice 5a approval ? iec 60950-1 (reinforced insulation) ? vde certification conformity ? vde 0884 part 10 ? cqc certification approval ? gb4943.1 key features ? single, dual, or high-side/low-side drivers ? single pwm or dual digital inputs ? high dv/dt immunity: ? 200 kv/s cmti ? 400 kv/s latch-up ? separate pull-up/down outputs for slew rate control ? wide supply range: ? input supply: 2.5C5.5 v ? driver supply: 4.2C30 v ? very low jitter of 200 ps p-p ? 60 ns propagation delay (max) ? dedicated enable pin ? silicon labs high performance isolation technology: ? industry leading noise immunity ? high speed, low latency and skew ? best reliability available ? compact packages: ? 8-pin soic ? 16-pin soic ? 5 x 5 mm lga-14 ? industrial temperature range: ? C40 to 125 c ? aec-q100 qualified silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 this information applies to a product under development. its characteristics and specifications are subject to change without notice.
1. ordering guide table 1.1. si827x ordering guide ordering part number inputs driver configuration output uvlo integrated deglitcher dead time adjustable range low jitter package isolation rating products available now SI8271AB-IS vi single 5 n n/a y soic-8 nb 2.5 kvrms si8271bb-is vi single 8 n n/a y soic-8 nb 2.5 kvrms si8271db-is vi single 12 n n/a y soic-8 nb 2.5 kvrms si8271gb-is vi single 3 n n/a y soic-8 nb 2.5 kvrms si8273ab-is1 via/vib hs/ls 5 n n/a y soic-16 nb 2.5 kvrms si8273abd-is1 via/vib hs/ls 5 y n/a n soic-16 nb 2.5 kvrms si8273ab-im via/vib hs/ls 5 n n/a y 5x5mm lga-14 2.5 kvrms si8273abd-im via/vib hs/ls 5 y n/a n 5x5mm lga-14 2.5 kvrms si8273db-is1 via/vib hs/ls 12 n n/a y soic-16 nb 2.5 kvrms si8273dbd-is1 via/vib hs/ls 12 y n/a n soic-16 nb 2.5 kvrms si8273gb-is1 via/vib hs/ls 3 n n/a y soic-16 nb 2.5 kvrms si8273gbd-is1 via/vib hs/ls 3 y n/a n soic-16 nb 2.5 kvrms si8273bb-is1 via/vib hs/ls 8 n n/a y soic-16 nb 2.5 kvrms si8273bbd-is1 via/vib hs/ls 8 y n/a n soic-16 nb 2.5 kvrms si8274ab1-is1 pwm hs/ls 5 n 10-200 y soic-16 nb 2.5 kvrms si8274ab4d-is1 pwm hs/ls 5 y 20-700 n soic-16 nb 2.5 kvrms si8274ab1-im pwm hs/ls 5 n 10-200 y 5x5mm lga-14 2.5 kvrms si8274ab4d-im pwm hs/ls 5 y 20-700 n 5x5mm lga-14 2.5 kvrms si8274bb1-is1 pwm hs/ls 8 n 10-200 y soic-16 nb 2.5 kvrms si8274db1-is1 pwm hs/ls 12 n 10-200 y soic-16 nb 2.5 kvrms si8274gb1-is1 pwm hs/ls 3 n 10-200 y soic-16 nb 2.5 kvrms si8274gb4d-is1 pwm hs/ls 3 y 20-700 n soic-16 nb 2.5 kvrms si8274gb1-im pwm hs/ls 3 n 10-200 y 5x5mm lga-14 2.5 kvrms si8274gb4d-im pwm hs/ls 3 y 20-700 n 5x5mm lga-14 2.5 kvrms si8275gb-is1 via/vib dual 3 n n/a y soic-16 nb 2.5 kvrms si8275gbd-is1 via/vib dual 3 y n/a n soic-16 nb 2.5 kvrms si8275ab-im via/vib dual 5 n n/a y 5x5mm lga-14 2.5 kvrms si827x data sheet ordering guide silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 1
ordering part number inputs driver configuration output uvlo integrated deglitcher dead time adjustable range low jitter package isolation rating si8275abd-im via/vib dual 5 y n/a n 5x5mm lga-14 2.5 kvrms contact silicon labs sales for these options si8271abd-is vi single 5 y n/a n soic-8 nb 2.5 kvrms si8271bbd-is vi single 8 y n/a n soic-8 nb 2.5 kvrms si8271dbd-is vi single 12 y n/a n soic-8 nb 2.5 kvrms si8271gbd-is vi single 3 y n/a n soic-8 nb 2.5 kvrms si8273bb-is1 via/vib hs/ls 8 n n/a y soic-16 nb 2.5 kvrms si8273bbd-is1 via/vib hs/ls 8 y n/a n soic-16 nb 2.5 kvrms si8274bb4d-is1 pwm hs/ls 8 y 20-700 n soic-16 nb 2.5 kvrms si8274db4d-is1 pwm hs/ls 12 y 20-700 n soic-16 nb 2.5 kvrms si8275ab-is1 via/vib dual 5 n n/a y soic-16 nb 2.5 kvrms si8275abd-is1 via/vib dual 5 y n/a n soic-16 nb 2.5 kvrms si8275bb-is1 via/vib dual 8 n n/a y soic-16 nb 2.5 kvrms si8275bbd-is1 via/vib dual 8 y n/a n soic-16 nb 2.5 kvrms si8275db-is1 via/vib dual 12 n n/a y soic-16 nb 2.5 kvrms si8275dbd-is1 via/vib dual 12 y n/a n soic-16 nb 2.5 kvrms si8275bb-im via/vib dual 8 n n/a y 5x5mm lga-14 2.5 kvrms si8275bbd-im via/vib dual 8 y n/a n 5x5mm lga-14 2.5 kvrms si8275db-im via/vib dual 12 n n/a y 5x5mm lga-14 2.5 kvrms si8275dbd-im via/vib dual 12 y n/a n 5x5mm lga-14 2.5 kvrms si8275gb-im via/vib dual 3 n n/a y 5x5mm lga-14 2.5 kvrms si8275gbd-im via/vib dual 3 y n/a n 5x5mm lga-14 2.5 kvrms si8275da-im via/vib dual 12 n n/a y 5x5mm lga-14 1 kvrms si8275dad-im via/vib dual 12 y n/a n 5x5mm lga-14 1 kvrms si827x data sheet ordering guide silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 2
2. system overview si8271 uvlo vdd vo+ gnda vddi vi isolation uvlo gndi vddi vddi en vo- figure 2.1. si8271 block diagram si8273 uvlo uvlo gndi vib vddi via vdda voa gnda vob vddi vddi isolation vddi vddb gndb en isolation uvlo overlap protection figure 2.2. si8273 block diagram si827x data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 3
si8274 uvlo uvlo gndi vddi pwm vdda voa gnda vob vddi vddi isolation vddi vddb gndb en isolation uvlo dt control & overlap protection dt lpwm lpwm figure 2.3. si8274 block diagram si8275 uvlo vdda voa gnda vob vddi isolation vddi vddb gndb uvlo via isolation uvlo gndi vib vddi vddi en figure 2.4. si8275 block diagram si827x data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 4
the operation of an si827x channel is analogous to that of an optocoupler and gate driver, except an rf carrier is modulated instead of light. this simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si827x channel is shown in the figure below. rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver dead time control 4 a peak gnd v dd driver figure 2.5. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driver. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. see figure 2.6 modulation scheme on page 5 for more details. input signal output signal modulation signal figure 2.6. modulation scheme si827x data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 5
2.1 typical operating characteristics the typical performance characteristics depicted in the figures below are for information purposes only. refer to table 4.1 electrical characteristics on page 16 for actual specification limits. figure 2.7. rise/fall time vs. supply voltage figure 2.8. propagation delay vs. supply voltage figure 2.9. supply current vs. supply voltage figure 2.10. supply current vs. supply voltage figure 2.11. supply current vs. temperature figure 2.12. rise/fall time vs. load si827x data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 6
figure 2.13. propagation delay vs. load figure 2.14. propagation delay vs. temperature figure 2.15. output sink current vs. temperature figure 2.16. output source current vs. temperature 2.2 family overview and logic operation during startup the si827x family of isolated drivers consists of single, high-side/low-side, and dual driver configurations. 2.2.1 products the table below shows the configuration and functional overview for each product in this family. table 2.1. si827x family overview part number configuration overlap protection programmable dead time inputs peak output current (a) si8271 single driver vi 4.0 si8273 high-side/low-side y via, vib 4.0 si8274 pwm y y pwm 4.0 si8275 dual driver via, vib 4.0 2.2.2 device behavior the table below consists of truth tables for the si8273, si8274, and si8275 families. si827x data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 7
table 2.2. si827x family truth table 1 si8271 (single driver) truth table inputs vddi state enable output notes vi vo+ voC l powered h hiCz l h powered h h hiCz x 2 unpowered x hiCz l x powered l hiCz l si8273 (high-side/low-side) truth table inputs vddi state enable output notes via vib voa vob l l powered h l l l h powered h l h h l powered h h l h h powered h l l invalid state. x 2 x 2 unpowered x l l output returns to input state within 7 s of vddi power restoration. x x powered l l l device is disabled. si8274 (pwm input high-side/low-side) truth table pwm input vddi state enable output notes voa vob h powered h h l l powered h l h x 2 unpowered x l l output returns to input state within 7 s of vddi power restoration. x powered l l l device is disabled. si8275 (dual driver) truth table inputs vddi state enable output notes via vib voa vob l l powered h l l l h powered h l h h l powered h h l h h powered h h h x 2 x 2 unpowered x l l output returns to input state within 7 s of vddi power restoration. x x powered l l l device is disabled. 1. this truth table assumes vdda and vddb are powered. if vdda and vddb are below uvlo, see 2.6.2 undervoltage lockout for more information. 2. an input can power the input die through an internal diode if its source has adequate current. si827x data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 8
2.3 power supply connections isolation requirements mandate individual supplies for vddi, vdda, and vddb. the decoupling caps for these supplies must be placed as close to the vdd and gnd pins of the si827x as possible. the optimum values for these capacitors depend on load current and the distance between the chip and the regulator that powers it. low effective series resistance (esr) capacitors, such as tantalum, are recommended. 2.4 power dissipation considerations proper system design must assure that the si827x operates within safe thermal limits across the entire load range.the si827x total power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by the series gate resistor and load. the equation below shows total si827x power dissipation. p d = ( v ddi )( i ddi ) + 2 ( i dd2 )( v dd2 ) + ( f ) ( q g ) ( v dd2 ) r p r p + r g + ( f )( q g )( v dd2 ) r n r n + r g + 2 fc int v dd2 2 where: p d is the total si827x device power dissipation (w) i ddi is the input-side maximum bias current (10 ma) i dd2 is the driver die maximum bias current (4 ma) c int is the internal parasitic capacitance (370 pf) v ddi is the input-side v dd supply voltage (2.5 to 5.5 v) v dd2 is the driver-side supply voltage (4.2 to 30 v) f is the switching frequency (hz) q g is the gate charge of external fet r g is the external gate resistor r p is the r ds(on) of the driver pull-up switch: 2.7 r n is the r ds(on) of the driver pull-down switch: 1 equation 1 power dissipation example for driver using equation 1 with the following givens: v ddi = 5.0 v v dd2 = 12 v f = 350 khz r g = 22 q g = 25 nc pd = 199 mw from which the driver junction temperature is calculated using equation 2, where: pd is the total si827x device power dissipation (w) ja is the thermal resistance from junction to air (105 c/w in this example) t a is the ambient temperature t j = p d j a + t a = ( 0.199)(105) + 20 = 41.0 c si827x data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 9
the maximum power dissipation allowable for the si827x is a function of the package thermal resistance, ambient temperature, and maximum allowable junction temperature, as shown in equation 2: p d max t j max ? t a j a where: p dmax = maximum si827x power dissipation (w) t jmax = si827x maximum junction temperature (150 c) t a = ambient temperature (20 c) ja = si827x junction-to-air thermal resistance (105 c/w) equation 2 substituting values for p dmax t jmax , t a , and ja into equation 2 results in a maximum allowable total power dissipation of 1.19 w. maxi- mum allowable load is found by substituting this limit and the appropriate data sheet values from table 4.1 electrical characteristics on page 16 into equation 1 and simplifying. the result is equation 3, both of which assume vddi = 5 v and vdda = vddb = 12 v. c l ( m a x ) = 1.24 10 ? 2 f ? 1.21 10 ? 9 equation 3 figure 2.17. max load vs. switching frequency 2.5 layout considerations it is most important to minimize ringing in the drive path and noise on the si827x vdd lines. care must be taken to minimize parasitic inductance in these paths by locating the si827x as close to the device it is driving as possible. in addition, the vdd supply and ground trace paths must be kept short. for this reason, the use of power and ground planes is highly recommended. a split ground plane sys- tem having separate ground and vdd planes for power devices and small signal components provides the best overall noise perform- ance. si827x data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 10
2.6 undervoltage lockout operation device behavior during start-up, normal operation and shutdown is shown in the figure below, where uvlo+ and uvlo- are the posi- tive-going and negative-going thresholds respectively. note: outputs voa and vob default low when input side power supply (vddi) is not present. 2.6.1 device startup outputs voa and vob are held low during power-up until vdd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs via and vib. 2.6.2 undervoltage lockout undervoltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. the input (control) side, driver a and driver b, each have their own undervoltage lockout monitors. the si827x input side enters uvlo when vddi < vddi uvC , and exits uvlo when vddi > vddi uv+ . the driver outputs, voa and vob, remain low when the input side of the si827x is in uvlo and their respective vdd supply (vdda, vddb) is within tolerance. each driver output can enter or exit uvlo independently. for example, voa unconditionally enters uvlo when vdda falls below vdda uvC and exits uvlo when vdda rises above vdda uv+ . the uvlo circuit unconditionally drives vo low when vdd is below the lockout threshold. upon power up, the si827x is maintained in uvlo until vdd rises above vdd uv+ . during power down, the si827x enters uvlo when vdd falls below the uvlo threshold plus hysteresis (i.e., vdd < vdd uv+ C vdd hys ). please refer to spec tables for uvlo values. via voa enable vddi uvlo- vdda tstart tstart tstart tsd trestart tphl tplh uvlo+ uvlo- uvlo+ tsd vdd hys vdd hys figure 2.18. device behavior during normal operation and shutdown 2.6.3 control inputs via, vib, and pwm inputs are high-true, ttl level-compatible logic inputs. a logic high signal on via or vib causes the corresponding output to go high. for pwm input versions (si8274), voa is high and vob is low when the pwm input is high, and voa is low and vob is high when the pwm input is low. si827x data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 11
2.6.4 enable input when brought low, the enable input unconditionally drives voa and vob low regardless of the states of via and vib. device opera- tion terminates within tsd after enable = v il and resumes within trestart after enable = v ih . the enable input has no effect if vddi is below its uvlo level (i.e., voa, vob remain low). 2.7 programmable dead time and overlap protection all pwm drivers (si8274x) include programmable dead time, which adds a user-programmable delay between transitions of voa and vob. when enabled, dead time is present on all transitions. the amount of dead time delay (dt) is programmed by a single resistor (rdt) connected from the dt input to ground per the equation below. d t = 2.02 rdt + 7.77 (for 10-200 ns range) d t = 6.06 rdt + 3.84 (for 20-700 ns range) where: dt = dead time (ns) and rdt = dead time programming resistor (k?) equation 4 input/output timing waveforms for the si8273 two-input drivers are shown in the figure below, and dead time waveforms for the si8274 are shown in figure 2.20 dead time waveforms for si8274 drivers on page 13. via vib voa vob a b c d e f g h i figure 2.19. input / output waveforms for si8273 drivers si827x data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 12
table 2.3. input / output waveforms for high-side / low-side two-input drivers ref description a normal operation: via high, vib low. b normal operation: vib high, via low. c contention: via = vib = high. d recovery from contention: via transitions low. e normal operation: via = vib = low. f normal operation: via high, vib low. g contention: via = vib = high. h recovery from contention: vib transitions low. i normal operation: vib transitions high. pwm lpwm (internal) voa vob dt dt 10% 10% 90% 90% 50% vob typical dead time operation figure 2.20. dead time waveforms for si8274 drivers 2.8 de-glitch feature a de-glitch feature is provided on some options, as defined in the 1. ordering guide . the internal de-glitch circuit provides an internal time delay of 15 ns typical, during which any noise is ignored and will not pass through the ic. for these product options, the propaga- tion delay will be extended by 15 ns, as specified in the spec table. si827x data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 13
3. applications the following examples illustrate typical circuit configurations using the si827x. 3.1 high-side/low-side driver in the figure below, side a shows the si8273 controlled using the via and vib input signals, and side b shows the si8274 controlled by a single pwm signal. si8273 cb 1500 v max via vdda voa gnda vob enable vdd2 controller vib out1 out2 i/o q1 q2 d1 c3 1 f si8274 cb pwm vdda voa gnda vob vddb gndb enable dt rdt controller pwmout i/o q1 q2 d1 a b vdd2 c3 1 f 1500 v max gndi vddi vddi c2 0.1 f c1 1 f vdd2 c4 0.1 f c5 10 f vddb gndb gndi vddi vddi c2 0.1 f c1 1 f vdd2 c4 0.1 f c5 10 f figure 3.1. si827x in half-bridge application for both cases, d1 and cb form a conventional bootstrap circuit that allows voa to operate as a high-side driver for q1, which has a maximum drain voltage of 1500 v. vob is connected as a conventional low-side driver. note that the input side of the si827x requires vdd in the range of 2.5 to 5.5 v, while the vdda and vddb output side supplies must be between 4.2 and 30 v with respect to their respective grounds. the boot-strap start up time will depend on the cb cap chosen. vdd2 is usually the same as vddb. also note that the bypass capacitors on the si827x should be located as close to the chip as possible. moreover, it is recommended that bypass ca- pacitors be used (as shown in the figures above for input and driver side) to reduce high frequency noise and maximize performance. the outputs voa and vob can be used interchangeably as high side or low side drivers. si827x data sheet applications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 14
3.2 dual driver the figure below shows the si827x configured as a dual driver. note that the drain voltages of q1 and q2 can be referenced to a com- mon ground or to different grounds with as much as 1500 v dc between them. si8275 gndi vddi via vdda voa gnda vob vddi vddb gndb enable controller vib out1 out2 i/o q2 vdda vddb c2 0.1 f c1 1 f c3 0.1 f c4 10 f c5 0.1 f c6 10 f q1 figure 3.2. si827x in a dual driver application because each output driver resides on its own die, the relative voltage polarities of voa and vob can reverse without damaging the driver. that is, the voltage at voa can be higher or lower than that of vob by vdd without damaging the driver. therefore, a dual driver in a high-side/low-side drive application can use either voa or vob as the high side driver. similarly, a dual driver can operate as a dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity changes. si827x data sheet applications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 15
4. electrical specifications table 4.1. electrical characteristics v ddi = 5 v, gndi = 0 v, vdda/b-gnda/b = 30 v, t a = C40 to +125 c; typical specs at 25 c parameter symbol test condition min typ max units dc parameters input supply voltage vddi 2.5 5.5 v driver supply voltage (vdda/b C gnda/b) 4.2 30 v input supply quiescent current iddi(q) 7.9 10.0 ma input supply active current iddi f = 500 khz 8.0 10.0 ma output supply quiescent current iddx(q) 2.5 4.0 ma output supply active current iddx f = 500 khz 10.0 11.0 ma gate driver high output transistor rds (on) r oh 2.7 low output transistor rds (?) r ol 1.0 high level peak output current i oh v dda/b = 15 v, see figure 4.2 ioh source current test circuit on page 19 for si827xg, v dd = 4.2 v, t < 250 ns 1.8 a low level peak output current i ol v dda/b = 15 v, see figure 4.1 iol sink current test cir- cuit on page 19 for si827xg, v dd = 4.2 v, t pw_iol < 250 ns 4.0 a uvlo vddi uvlo threshold + vddi uv+ 1.85 2.2 2.45 v vddi uvlo threshold C vddi uvC 1.75 2.1 2.35 v vddi hysteresis vddi hys 100 mv uvlo threshold + (driver side) 3 v threshold vddx uv+ 2.7 3.5 4.0 v 5 v threshold 4.9 5.5 6.3 v 8 v threshold 7.2 8.3 9.5 v 12 v threshold 11 12.2 13.5 v uvlo threshold - (driver side) si827x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 16
parameter symbol test condition min typ max units 3 v threshold vddx uv- 2.5 3.2 3.8 v 5 v threshold 4.6 5.2 5.9 v 8 v threshold 6.7 7.8 8.9 v 12 v threshold 9.6 10.8 12.1 v uvlo lockout hysteresis 3 v threshold vdd hys 300 mv 5 v threshold 300 mv 8 v threshold 500 mv 12 v threshold 1400 mv digital logic high input threshold vih 2.0 v logic low input threshold vil 0.8 v input hysteresis vihyst 350 400 mv logic high output voltage voh io = C1 ma vdda/b C 0.04 v logic low output voltage vol io = 1 ma 0.04 v ac switching parameters propagation delay si8271/3/5 with low jitter t plh , t phl c l = 200 pf 20 30 60 ns propagation delay si8271/3/5 with de-glitch option t plh, t phl c l = 200 pf 30 45 75 ns propagation delay si8274 with low jitter t phl c l = 200 pf 20 30 60 ns propagation delay si8274 with de-glitch option t phl c l = 200 pf 30 45 75 ns propagation delay si8274 with low jitter t plh c l = 200 pf 30 45 75 ns propagation delay si8274 with de-glitch option t plh c l = 200 pf 65 85 105 ns pulse width distortion si8271/3/5 all options pwd |tplh C tphl| 3.6 8 ns pulse width distortion si8274 with low jitter pwd |tplh C tphl| 14 19 ns pulse width distortion si8274 with de-glitch option pwd |tplh C tphl| 38 47 ns peak to peak jitter si827x with low jitter 200 ps si827x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 17
parameter symbol test condition min typ max units programmed dead-time (dt) for products with 10C200 ns dt range dt rdt = 6 k 10 20 30 ns rdt = 15 k 26 38 50 rdt = 100 k 150 210 260 programmed dead-time (dt) for products with 20C700 ns dt range dt rdt = 6 k 23 40 57 ns rdt = 15 k 60 95 130 rdt = 100 k 450 610 770 rise time t r cl = 200 pf 4 10.5 16 ns fall time t f cl = 200 pf 5.5 13.3 18 ns device startup time t start 16 30 s common mode transient immunity si827x with de-glitch option see figure 4.3 com- mon mode transient immunity test circuit on page 20 . vcm = 1500 v 200 350 400 kv/s common mode transient immunity si827x with low jitter option see figure 4.3 com- mon mode transient immunity test circuit on page 20 . vcm = 1500 v 150 300 400 kv/s si827x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 18
4.1 test circuits the figures below depict sink current, source current, and common-mode transient immunity test circuits. input 1 f 100 f 10 rsns 0.1 si827x 1 f cer 10 f el vdda = vddb = 15 v in out gnd vdd schottky 50 ns 200 ns measure input waveform gnd vddi vddi 8 v + _ figure 4.1. iol sink current test circuit input 1 f 100 f 10 rsns 0.1 si827x 1 f cer 10 f el vdda = vddb = 15 v in out gnd vdd 50 ns 200 ns measure input waveform gnd vddi schottky vddi 5.5 v + _ figure 4.2. ioh source current test circuit si827x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 19
oscilloscope 5v isol a ted supply vdda voa gnda 12 v supply high voltage surge generator vcm surge output 100k high voltage differential probe vddb vob gndb dt gndi vddi input en input signal switch input output isolated gr ound si827x the si827x is certified under csa component acceptance notice 5a. for more details, see file 232873. 60950-1: up to 125 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. vde the si827x is certified according to vde 0884-10. for more details, see file 5006301-4880-0001. vde 0884-10: up to 630 v peak for basic insulation working voltage. ul the si827x is certified under ul1577 component recognition program. for more details, see file e257455. rated up to 2500 v rms isolation voltage for basic protection. cqc the si827x is certified under gb4943.1-2011. rated up to 125 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 1. regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. 2. for more information, see 1. ordering guide. si827x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 20
table 4.3. insulation and safety-related specifications parameter symbol test condition value unit soic-8 nb soic-16 14 ld lga nominal air gap (clearance) l(1o1) 4.7 4.7 3.5 mm nominal external tracking (creepage) l(1o2) 3.9 3.9 3.5 mm minimum internal gap (internal clearance) 0.008 0.008 0.008 mm tracking resistance (proof tracking index) pti iec60112 600 600 600 v erosion depth ed 0.019 0.019 0.021 mm resistance (input-output) 1 r io 10 12 10 12 10 12 capacitance (input-output) 1 c io f = 1 mhz 0.5 0.5 0.5 pf input capacitance 2 c i 3.0 3.0 3.0 pf notes: 1. to determine resistance and capacitance, the si827x is converted into a 2-terminal device. all pins on side 1 are shorted to cre- ate terminal 1, and all pins on side 2 are shorted to create terminal 2. the parameters are then measured between these two terminals. 2. measured from input pin to ground. table 4.4. iec 60664-1 ratings parameter test condition specification soic-8 nb soic-16 14 ld lga basic isolation group material group i i i installation classification rated mains voltages < 150 v rms i-iv i-iv i-iv rated mains voltages < 300 v rms i-iii i-iii i-iii rated mains voltages < 400 v rms i-ii i-ii i-ii rated mains voltages < 600 v rms i-ii i-ii i-ii si827x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 21
table 4.5. vde 0884 insulation characteristics 1 parameter symbol test condition characteristic unit maximum working insulation voltage v iorm 630 v peak input to output test voltage v pr method b1 (v iorm x 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1181 v peak transient overvoltage v iotm t = 60 sec 4000 v peak pollution degree (din vde 0110, table 1) 2 insulation resistance at t s , v io = 500 v r s >10 9 note: 1. maintenance of the safety data is ensured by protective circuits. the si827x provides a climate classification of 40/125/21. table 4.6. iec safety limiting values 1 parameter symbol test condition soic-8 nb soic-16 14 ld lga unit case temperature t s 140 150 150 c safety input current s ja = 110 c/w (soic-8), 105 c/w (nb soic-16, 14 ld lga), vddi = 5.5 v, v dda = v ddb = 30 v, t j = 150 c, t a = 25 c 35 40 40 ma device power dissipation p d 1 1.2 1.2 note: 1. maximum value allowed in the event of a failure. refer to the thermal derating curve in the two figures below. si827x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 22
table 4.7. thermal characteristics parameter symbol soic-8 nb soic-16 14 ld lga unit ic junction-to-air thermal resistance ja 110 105 105 c/w 0 200 150 100 50 60 40 20 0 case temperature (oc) safety-limiting current (ma) vddi = 5.5 v vdda, vddb = 30 v 10 30 50 figure 4.4. nb soic-16, lga-14 thermal derating curve, dependence of safety limiting values limiting values with case temperature per vde 0884 0 200 140 100 60 60 40 20 0 case temperature (oc) safety-limiting current (ma) 10 30 50 vddi = 5.5 v vdda, vddb = 30 v figure 4.5. nb soic-8 thermal derating curve, dependence of safety limiting values limiting values with case temperature per vde 0884 si827x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 23
table 4.8. absolute maximum ratings 1 parameter symbol min max units storage temperature t stg C65 +150 c operating temperature t a C40 +125 c junction temperature t j +150 c input-side supply voltage vddi C0.6 6.0 v driver-side supply voltage vdda, vddb C0.6 36 v voltage on any pin with respect to ground v io C0.5 vdd + 0.5 v peak output current (t pw = 10 s, duty cycle = 0.2%) i opk 4.0 a lead solder temperature (10 s) 260 c hbm rating esd 3.5 kv cdm 2000 v maximum isolation voltage (input to output) (1 sec) nb soic-16 and soic-8 3000 v rms maximum isolation voltage (input to output) (1 sec) 5x5 lga-14 3000 v rms maximum isolation voltage (output to output) (1 sec) nb soic-16 1500 v rms maximum isolation voltage (output to output) (1 sec) 5x5 lga-14 650 v rms latch-up immunity 400 kv/s note: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions specified in the operational sections of this data sheet. si827x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 24
5. pin descriptions 5.1 si8271 pin descriptions si8271 vdd vo+ vo- gnd vddi vi gndi en 1 2 3 4 8 7 6 5 figure 5.1. pin assignments si8271 table 5.1. si8271 pin descriptions pin name description 1 vi digital driver control signal 2 vddi input side power supply 3 gndi input side ground 4 en enable 5 gnd driver side ground 6 voC gate drive pull low 7 vo+ gate drive pull high 8 vdd driver side power supply si827x data sheet pin descriptions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 25
5.2 si8273/75 pin descriptions si8273 si8275 vdda voa gnda nc nc vddb vob gndb vddi via vib gndi nc en nc vddi 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 si8273 si8275 1 2 3 4 5 6 7 14 13 12 11 10 9 8 vib nc via gndi nc en vddi vdda voa gnda nc vddb vob gndb figure 5.2. pin assignments si8273/5 table 5.2. si8273/5 pin descriptions nb soic-16 pin # 5x5 mm lga-14 pin # name description 1 2 via digital driver control signal for a driver 2 3 vib digital driver control signal for b driver 3,8 7 vddi input side power supply 4 4 gndi input side ground 5 5 en enable 6, 7, 12, 13 1, 6, 11 nc no connect 9 8 gndb driver side power supply for b driver 10 9 vob gate drive output for b driver 11 10 vddb driver side power supply for b driver 14 12 gnda driver side power supply for a driver 15 13 voa gate drive output for a driver 16 14 vdda driver side power supply for a driver si827x data sheet pin descriptions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 26
5.3 si8274 pin descriptions si8274 vdda voa gnda nc nc vddb vob gndb vddi pwm nc gndi dt en nc vddi 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 si8274 1 2 3 4 5 6 7 14 13 12 11 10 9 8 nc nc pwm gndi dt en vddi vdda voa gnda nc vddb vob gndb figure 5.3. pin assignments si8274 table 5.3. si8274 pin descriptions nb soic-16 pin # 5x5 mm lga-14 pin # name description 1 2 pwm pulse width modulated driver control signal 2, 7, 12, 13 1, 3, 11 nc no connect 3, 8 7 vddi input side power supply 4 4 gndi input side ground 5 5 en enable 6 6 dt dead time control 9 8 gndb driver side power supply for b driver 10 9 vob gate drive output for b driver 11 10 vddb driver side power supply for b driver 14 12 gnda driver side power supply for a driver 15 13 voa gate drive output for a driver 16 14 vdda driver side power supply for a driver si827x data sheet pin descriptions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 27
6. package outlines 6.1 package outline: 16-pin narrow-body soic the figure below illustrates the package details for the si827x in a 16-pin narrow-body soic (so-16). the table below lists the values for the dimensions shown in the illustration. figure 6.1. 16-pin small outline integrated circuit (soic) package si827x data sheet package outlines silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 28
table 6.1. package diagram dimensions dimension min max dimension min max a 1.75 l 0.40 1.27 a1 0.10 0.25 l2 0.25 bsc a2 1.25 h 0.25 0.50 b 0.31 0.51 0 8 c 0.17 0.25 aaa 0.10 d 9.90 bsc bbb 0.20 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.25 e 1.27 bsc 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si827x data sheet package outlines silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 29
6.2 package outline: 8-pin narrow body soic the figure below illustrates the package details for the si827x in an 8-pin narrow-body soic package. the table below lists the values for the dimensions shown in the illustration. figure 6.2. 8-pin narrow body soic package si827x data sheet package outlines silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 30
table 6.2. 8-pin narrow body soic package diagram dimensions symbol millimeters min max a 1.35 1.75 a1 0.10 0.25 a2 1.40 ref 1.55 ref b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27 bsc h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 0 8 si827x data sheet package outlines silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 31
6.3 package outline: 14 ld lga (5 x 5 mm) the figure below illustrates the package details for the si827x in an lga outline. the table below lists the values for the dimensions shown in the illustration. figure 6.3. si827x lga outline table 6.3. package diagram dimensions dimension min nom max a 0.74 0.84 0.94 b 0.25 0.30 0.35 d 5.00 bsc d1 4.15 bsc e 0.65 bsc e 5.00 bsc e1 3.90 bsc l 0.70 0.75 0.80 l1 0.05 0.10 0.15 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.15 eee 0.08 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. si827x data sheet package outlines silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 32
7. land patterns 7.1 land pattern: 16-pin narrow body soic the figure below illustrates the recommended land pattern details for the si827x in a 16-pin narrow-body soic. the table below lists the values for the dimensions shown in the illustration. figure 7.1. 16-pin narrow body soic pcb land pattern table 7.1. 16-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. si827x data sheet land patterns silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 33
7.2 land pattern: 8-pin narrow body soic the figure below illustrates the recommended land pattern details for the si827x in an 8-pin narrow-body soic. the table below lists the values for the dimensions shown in the illustration. figure 7.2. 8-pin narrow body soic land pattern table 7.2. 8-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x173-8n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. si827x data sheet land patterns silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 34
7.3 land pattern: 14 ld lga the figure below illustrates the recommended land pattern details for the si827x in a 14-pin lga. the table below lists the values for the dimensions shown in the illustration. figure 7.3. 14-pin lga land pattern table 7.3. 14-pin lga land pattern dimensions dimension (mm) c1 4.20 e 0.65 x1 0.80 y1 0.40 notes: 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabri- cation allowance of 0.05 mm. 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 5. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1. 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si827x data sheet land patterns silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 35
8. top markings 8.1 si827x top marking (16-pin narrow body soic) table 8.1. top marking explanation (16-pin narrow body soic) line 1 marking: base part number ordering options see 1. ordering guide for more information. si827 = isodriver product series y = configuration 3 = high-side/low-side (hs/ls) 4 = pwm hs/ls 5 = dual driver u = uvlo level g = 3 v a = 5 v b = 8 v d = 12 v v = isolation rating b = 2.5 kv w = dead-time setting range 1= 10-200 ns 4 = 20-700 ns x = integrated de-glitch circuit d = integrated none = not included line 2 marking: yy = year ww = workweek assigned by the assembly house. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. si827x data sheet top markings silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 36
8.2 si8271 top marking (8-pin narrow body soic) table 8.2. top marking explanation (narrow body soic) line 1 marking: customer part number si827 = isodriver product series y = configuration 1 = single driver u = uvlo level g = 3 v a = 5 v b = 8 v d = 12 v v = isolation rating b = 2.5 kv line 2 marking: wx = ordering options w = dead-time setting range 1= 10-200 ns 4 = 20-700 ns x = integrated de-glitch circuit d = integrated none = not included yy = year ww = work week assigned by the assembly house. corresponds to the year and workweek of the mold date. line 3 marking: tttttt = mfg code manufacturing code from assembly purchase order form. si827x data sheet top markings silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 37
8.3 si827x top marking (14 ld lga) table 8.3. top marking explanation (14 ld lga) line 1 marking: base part number ordering options see 1. ordering guide for more information. si827 = isodriver product series y = configuration 1 = single driver 3 = high-side/low-side (hs/ls) 4 = pwm hs/ls 5 = dual driver line 2 marking: ordering options u = uvlo level g = 3 v a = 5 v b = 8 v d = 12 v v = isolation rating b = 2.5 kv w = dead-time setting range 1= 10-200 ns 4 = 20-700 ns x = integrated de-glitch circuit d = integrated none = not included line 3 marking: tttttt = mfg code manufacturing code from assembly. line 4 marking: circle = 1.5 mm diameter pin 1 identifier. yyww manufacturing date code. si827x data sheet top markings silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 38
9. revision history 9.1 revision 0.1 february 26, 2016 ? initial release. si827x data sheet revision history silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 39
table of contents 1. ordering guide ..............................1 2. system overview ..............................3 2.1 typical operating characteristics .......................6 2.2 family overview and logic operation during startup ................7 2.2.1 products ...............................7 2.2.2 device behavior ............................7 2.3 power supply connections .........................9 2.4 power dissipation considerations .......................9 2.5 layout considerations ........................... 10 2.6 undervoltage lockout operation ....................... 11 2.6.1 device startup ............................. 11 2.6.2 undervoltage lockout .......................... 11 2.6.3 control inputs ............................. 11 2.6.4 enable input .............................. 12 2.7 programmable dead time and overlap protection ................. 12 2.8 de-glitch feature ............................. 13 3. applications ............................... 14 3.1 high-side/low-side driver ......................... 14 3.2 dual driver ............................... 15 4. electrical specifications .......................... 16 4.1 test circuits .............................. 19 4.2 regulatory information (pending) ....................... 20 5. pin descriptions ............................. 25 5.1 si8271 pin descriptions .......................... 25 5.2 si8273/75 pin descriptions ......................... 26 5.3 si8274 pin descriptions .......................... 27 6. package outlines ............................. 28 6.1 package outline: 16-pin narrow-body soic ................... 28 6.2 package outline: 8-pin narrow body soic .................... 30 6.3 package outline: 14 ld lga (5 x 5 mm) ..................... 32 7. land patterns .............................. 33 7.1 land pattern: 16-pin narrow body soic ..................... 33 7.2 land pattern: 8-pin narrow body soic ..................... 34 7.3 land pattern: 14 ld lga .......................... 35 8. top markings .............................. 36 8.1 si827x top marking (16-pin narrow body soic) .................. 36 8.2 si8271 top marking (8-pin narrow body soic) .................. 37 table of contents 40
8.3 si827x top marking (14 ld lga) ....................... 38 9. revision history ............................. 39 9.1 revision 0.1 .............................. 39 table of contents 41
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